Moore’s Law and uProcessor Technology

For many years Moore’s law which held that the most economic per unit transistor density on an integrated circuit would double every two years held true. In fact, for much of that time it doubled every 18 months. Note that this is the most economic per transistor not the maximum physically possible.

Recently, Moore’s law has stalled. You may have noticed there hasn’t been a noticeable increase in CPU speeds for the last year or so. Manufacturers, unable to economically scale CPU speeds, have gone to multiple core CPU’s.

IBM has promised an 80 core multi-core CPU within five years. Parallel processing has it’s advantages and limitations. The human brain relies on massive parallel processing to overcome the speed limitations of individual neurons and when you consider the huge amount of information the human brain processes, it does quite well.

However, not all tasks lend themselves to parallel processing and those that do require special programming. The human brain gets around this problem by being largely self-programming. That is, neural nets self-train and essentially wire themselves and adjust weightings of individual connections to produce the right results.

So far we haven’t really got this capability in silicon except for some crude neural network chips that attempt to emulate (poorly) neurons and only a very small number of them at that.

For the foreseeable future, parallel processing computers will need to be programmed specifically to use those parallel processors. Some tasks, like encryption key breaking, weather prediction, graphics rendering, shaped charge explosives design, protein folding problems, many of these tasks do lend themselves well to parallel computing, but many other tasks require an intermediate answer to be obtained before the next step can proceed and these tasks do not lend themselves well to parallel processing. These tasks require a single instruction execution unit with a faster clock speed to gain performance.

Heat has become the limiting factor in increasing CPU clock speeds. For years, making components smaller allowed faster speeds because power was dissipated primarily during switching, so the faster transistors switched on or off, the more heat was lost.

As the size of the transistors were reduced, a point was reached where the gates of the transistors became so small that the leakage current through the gate became the predominate source of heat and shrinking components further no longer allowed faster operational speeds.

About 80% of the dissipated power comes from this gate leakage current with CPU’s made with current 65 nanometer line width technology. The gate insulator on these transistors is just five atoms wide.

Intel will be coming out with new CPU’s later this year based upon 45 nanometer line width technology. To address the problem of gate leaking, Intel will be substituting a compound made with hafnium for the current silicon dioxide gate insulator. In addition they are using a metal other than silicon (but they aren’t specific) for the gate structure. Combined, these two things will greatly reduce gate leakage and thus power demands and will allow faster speeds as a result of the reduced heat production.

Interestingly, IBM is also coming out with a new hafnium based gate insulating material for their transition to 45nm design line processors. It seems difficult to believe that Intel and IBM came up with the same solution independently. They announced this development independently on the same day, January 26, 2007, as competing developments. They also will be replacing the polysilicon gate with another metal compound.

Both Intel and IBM have working 45nm processor prototypes running Vista, MacOS and others to demonstrate the functionality of this technology.

AMD is taking a different approach although they may ultimately incorporate hafnium based gate insulators in later 45nm production. IBM and AMD are required to share some information as part of a former legal settlement.

AMD is experimenting with making the transistor gates out of nickel rather than silicon. This allows a thicker gate insulator to be used and still obtain the same control over current flow through the gate.

AMD is also experimenting with “strained silicon” gates. They embed a certain number of germanium atoms within the silicon lattice to stretch it and force the atoms to be farther apart. This allows electronics to move more freely resulting in greater conductivity, higher drive currents, and thus results in faster speeds, up to 20-25% faster. This work is being done in conjunction with IBM.

AMD is also experimenting with adding a silicon on insulator layer that reduces leaking by eliminating stray electron carriers from the chip.

Lastly, AMD is looking into various multi-gate FET transistors that may have some advantages over conventional single gate IGFET’s.

It appears that, although Moore’s law took a temporary break, it is back on track at least for another decade or so. Ultimately these new technologies are expected to also enable a move to 32nm and then later 24nm line width designs. Maybe then we can have accurate weather forecasts.

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